Remove them flips

This commit is contained in:
2026-03-30 13:31:32 +02:00
parent 24c6140b9d
commit d01db89fb0

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@@ -34,10 +34,10 @@ carryFlagPosition = 4
instance Convert FlagRegister Word8 where instance Convert FlagRegister Word8 where
convert r = convert r =
(flip shiftL zeroFlagPosition $ if r ^. zero then 1 else 0) + ((`shiftL` zeroFlagPosition) $ if r ^. zero then 1 else 0) +
(flip shiftL subtractFlagPosition $ if r ^. subtract then 1 else 0) + ((`shiftL` subtractFlagPosition) $ if r ^. subtract then 1 else 0) +
(flip shiftL halfCarryFlagPosition $ if r ^. halfCarry then 1 else 0) + ((`shiftL` halfCarryFlagPosition) $ if r ^. halfCarry then 1 else 0) +
(flip shiftL carryFlagPosition $ if r ^. carry then 1 else 0) ((`shiftL` carryFlagPosition) $ if r ^. carry then 1 else 0)
instance Convert Word8 FlagRegister where instance Convert Word8 FlagRegister where
convert w = convert w =
@@ -153,7 +153,7 @@ execute cpu = \case
(new, FlagRegister {..}) (new, FlagRegister {..})
fetch :: CPU -> Word16 -> Word8 fetch :: CPU -> Word16 -> Word8
fetch _cpu addr = flip V.index (fromIntegral addr) $ _cpu ^. bus fetch _cpu addr = (`V.index` (fromIntegral addr)) $ _cpu ^. bus
write :: CPU -> Word16 -> Word8 -> CPU write :: CPU -> Word16 -> Word8 -> CPU
write _cpu target value = _cpu & bus %~ (flip V.update $ V.singleton (fromIntegral target, value)) write _cpu target value = _cpu & bus %~ (`V.update` V.singleton (fromIntegral target, value))